The present invention relates to a liquid crystal display device and a fabrication method for the liquid crystal display device, and more particularly, it relates to an active matrix type liquid crystal display device including thin film transistors and a fabrication method for the same.
Recently, an active matrix type liquid crystal display device is widely used as a display device for a personal computer, a thin television set, a display for a video imaging device or a digital camera, or the like. An equivalent circuit of one pixel of an active matrix type liquid crystal display device including a thin film transistor as an active element (hereinafter referred to as the xe2x80x9cTFT type liquid crystal display devicexe2x80x9d) is shown in FIG. 6. An area where pixels (pixel regions) are arranged in the form of a matrix corresponds to a display region.
In the TFT type liquid crystal display device, each pixel includes a thin film transistor (hereinafter referred to as the xe2x80x9cTFTxe2x80x9d), and a liquid crystal capacitor CLC and a storage capacitor CS connected to the drain D of the TFT. The liquid crystal capacitor CLC and the storage capacitor CS are together designated as a pixel capacitor Cpix. To the gate G of the TFT, a gate line (scanning line) is connected, and to the source S thereof, a source line (signal line) is connected. During a period when a scan signal is applied to the gate G (i.e., during one scan period), a signal voltage applied from the source line to the source S of the TFT is applied to a drain side electrode of the liquid crystal capacitor CLC (hereinafter referred to as the xe2x80x9cpixel electrodexe2x80x9d) and a drain side electrode of the storage capacitor CS (hereinafter referred to as the xe2x80x9cstorage capacitor electrodexe2x80x9d). On the other hand, to another electrode of the liquid crystal capacitor CLC (hereinafter referred to as the xe2x80x9ccounter electrodexe2x80x9d) and another electrode of the storage capacitor CS (hereinafter referred to as the xe2x80x9cstorage capacitor counter electrodexe2x80x9d), a predetermined counter voltage (common voltage) is applied through a counter electrode or storage capacitor counter electrode line (common line) COM. The storage capacitor counter electrode line COM formed on a TFT substrate is electrically connected to a counter electrode formed on a counter substrate. A net voltage applied to the liquid crystal capacitor CLC corresponds to a difference between the signal voltage and the counter voltage. The alignment of liquid crystal is changed in accordance with this voltage, so as to obtain a display state corresponding to the signal voltage.
In a period when a scan signal is not applied to the gate G (namely, when a TFT connected to another gate line is selected), the liquid crystal capacitor CLC and the storage capacitor CS are electrically insulated from the source line by the TFT. Until the TFT of interest is selected next, the liquid crystal capacitor CLC and the storage capacitor CS keep the predetermined display state by keeping the previously applied voltage. When the voltage holding property of the TFT and the pixel capacitor Cpix is low during this period, the display quality is degraded.
In order to attain a desired voltage holding property, a storage capacitor CS having a comparatively large capacitance value is sometimes required. When the areas of the storage capacitor electrode and the storage capacitor counter electrode are increased in order to increase the capacity of the storage capacitor CS, the aperture ratio can be degraded in a transmission type liquid crystal display device because these electrodes are generally formed from opaque materials.
Japanese Laid-Open Patent Publication No. 5-61071 discloses a TFT type liquid crystal display device using a storage capacitor having large capacity in a pixel. FIGS. 7A through 7C are cross-sectional views for showing procedures for forming a TFT and the storage capacitor of the liquid crystal display device described in this publication.
According to the publication, a groove (trench) 122 is formed in the surface of an insulating substrate 121 on which a TFT is to be formed, and the storage capacitor (capacity component) is formed in this groove 122. Furthermore, the storage capacitor is formed from a first electrode 123 formed integrally with a semiconductor layer of the TFT in the same procedure, a second electrode 126a formed from the same material as a gate electrode of the TFT and insulating films 124a and 125a formed from the same material as a gate insulating layer of the TFT. Thus, the structure and the fabrication process are simplified.
The TFT substrate including the TFT and the storage capacitor part shown in FIGS. 7A through 7C are fabricated as follows:
(1) A groove 122 is formed in the surface of a quartz substrate 121 through wet etching using a mixture of HF and NH4F (1:6) as an etchant.
(2) A first polysilicon layer 123 with a thickness of 80 nm is formed by the low pressure CVD. Silicon is implanted into the first polysilicon layer 123 twice at energy of 30 keV and dose of 1xc3x971015/cm2 and at energy of 50 keV and dose of 1xc3x971015/cm2, respectively. The resultant is subjected to solid phase annealing, and part of the first polysilicon layer 123 is removed by etching.
(3) The first polysilicon layer 123 is thermally oxidized at 1000xc2x0 C., thereby forming a SiO2 film 124 with a thickness of 50 nm in the surface thereof. A part of the first polysilicon layer 123 not oxidized is ultimately formed into a first electrode of the storage capacitor and the semiconductor layer (the source, the channel and the drain) of the TFT.
(4) With an area of the SiO2 film 124 where the TFT is to be formed protected by a resist layer, arsenic ions (As+) are implanted at energy of 30 kev and dose of 5xc3x971015/cm2 into the part of the first polysilicon layer 123 to be formed into the first electrode of the storage capacitor.
(5) After removing the resist layer, a SiN film 125 with a thickness of 30 nm is formed by the low pressure CVD so as to cover the SiO2 film 124.
(6) A second polysilicon layer 126 with a thickness of 350 nm is formed on the entire surface of the substrate by the low pressure CVD, and the resistance is reduced by PSG.
(7) The second polysilicon layer 126 and the SiN film 125 are patterned by using a gas including CF4 and O2 (95:5), thereby forming a gate electrode 126b of the TFT, a second electrode 126a of the storage capacitor, a SiN gate insulating layer 125b and a storage capacitor SiN film 125a. Then, arsenic ions are implanted through the SiO2 film 124 into the first polysilicon layer 123 included in the TFT at energy of 160 keV and dose of 1xc3x971015/cm2, thereby forming an LDD (lightly doped drain).
(8) A resist is formed so as to cover the second electrode 126b, and arsenic ions are implanted at energy of 140 keV and dose of 2xc3x971015/cm2, thereby forming an n-channel. After removing the resist, another resist is formed on the entire surface, and boron ions (B+) are implanted at energy of 30 keV and dose of 2xc3x971015/cm2, thereby forming a p-channel.
(9) After removing the resist, an interlayer insulating film 131 of phosphorus silica glass (PSG) is formed by the low pressure CVD.
(10) A first contact hole 132 is formed in the interlayer insulating film 131 and the SiO2 film 124 by the wet etching using the mixture of HF and NH4F.
(11) An ITO (indium tin oxide) film 129 with a thickness of 140 nm is formed by sputtering at 400xc2x0 C. The ITO film 129 is wet etched by using an etchant including HCl, H2O and HNO3 (300:300:50), thereby patterning the ITO film 129. Then, by using a resist as a mask, a second contact hole 134 is formed in the ITO film 129 by the wet etching using the mixture of HF and NH4F.
(12) An AlSi layer with a thickness of 600 nm is deposited by sputtering on the entire surface, and the AlSi layer is patterned into an electrode 130 by the wet etching using a mixture of H3PO4 and H2O (2:10). Then, a passivation film 133 of SiN with a thickness of400 nm is formed by the atmospheric pressure CVD. The passivation film 133 is patterned by the plasma etching using a gas including CF4 and O2 (95:5).
The capacitance value of the storage capacitor of the liquid crystal display device disclosed in the above-described publication depends upon the dimension of the opening of the groove, the depth of the groove, the kind (dielectric constant) of material used for forming a dielectric layer and the thickness of the dielectric layer. The most significant factor in forming the storage capacitor having a desired capacitance value in this conventional technique is control of the depth of the groove. Since the groove is formed by etching the surface of the substrate made from a single material, the depth of the groove is controlled by adjusting the etch time. Even when the etch time is accurately adjusted, however, the depth of the groove may be varied if the etching rate is varied. Variation in the capacitance value of the storage capacitor degrades the display quality of the liquid crystal display device.
When the capacitance value is small, the storage capacitor can store small charge. Therefore, the storage capacitor is largely affected by a leakage current flowing through the TFT and hence cannot keep the predetermined voltage. On the contrary, when the capacitance value of the storage capacitor is large, the storage capacitor cannot be sufficiently charged, and hence, the predetermined voltage cannot be applied to the ends of the storage capacitor and the liquid crystal capacitor.
The present invention was devised to overcome the aforementioned conventional problems, and a main object is providing a liquid crystal display device and a fabrication method for the same in which the capacitance value of a storage capacitor is minimally varied so as to attain high display quality.
The liquid crystal display device of this invention including an insulating substrate, a thin film transistor formed on the insulating substrate, and a pixel electrode and a storage capacitor electrically connected to the thin film transistor, includes a first conductive layer formed on the insulating substrate; a first insulating layer formed on the first conductive layer and having an opening for exposing a part of the first conductive layer; a second conductive layer formed on the first conductive layer at least within the opening; a second insulating layer for covering the second conductive layer; and a third conductive layer for covering the second insulating layer at least within the opening, wherein the storage capacitor is formed from a stacked layer structure including the second conductive layer, the second insulating layer and the third conductive layer. Thus, the aforementioned object is achieved.
In the liquid crystal display device, the second conductive layer can be in contact with the first conductive layer within the opening.
The liquid crystal display device may further include a third insulating layer formed between the first conductive layer and the second conductive layer, and the first conductive layer and the second conductive layer can be electrically insulated from each other.
In the liquid crystal display device, the first conductive layer and the third conductive layer may be electrically connected to each other, and the storage capacitor can be formed from a stacked layer structure including the first conductive layer, the third insulating layer and the second conductive layer, and another stacked layer structure including the second conductive layer, the second insulating layer and the third conductive layer.
In the liquid crystal display device, the first conductive layer and the third conductive layer are preferably mutually connected within a contact hole formed in the first insulating layer in a position outside of a display region.
The liquid crystal display device may further include a shielding layer formed over at least a channel of the thin film transistor, and the shielding layer and the first conductive layer may be formed from the same film and electrically insulated from each other.
In the liquid crystal display device, a gate insulating layer of the thin film transistor is preferably formed from a film the same as a film used for forming the second insulating layer.
In the liquid crystal display device, a channel, a source and a drain of the thin film transistor are preferably formed in a film the same as a film used for forming the second conductive layer.
In the liquid crystal display device, a gate electrode of the thin film transistor is preferably formed from a film the same as a film used for forming the third conductive layer.
The method of this invention of fabricating a liquid crystal display device including an insulating substrate, a thin film transistor formed on the insulating substrate, and a pixel electrode and a storage capacitor electrically connected to the thin film transistor, includes the steps of forming a first conductive layer on the insulating substrate; forming a first insulating layer on the first conductive layer; forming an opening for exposing a part of the first conductive layer in the first insulating layer by etching the first insulating layer with the first conductive layer used as an etch-stop layer; forming a second conductive layer on the first conductive layer at least within the opening; forming a second insulating layer for covering the second conductive layer; and forming a third conductive layer for covering the second insulating layer at least with in the opening, wherein the storage capacitor is formed from a stacked layer structure including the second conductive layer, the second insulating layer and the third conductive layer. Thus, the aforementioned object is achieved.
The method of fabricating a liquid crystal display device may further include the steps of forming, between the first conductive layer and the second conductive layer, a third insulating layer for electrically insulating the first conductive layer and the second conductive layer from each other; and electrically connecting the first conductive layer and the third conductive layer to each other, and the storage capacitor can be formed from a stacked layer structure including the first conductive layer, the third insulating layer and the second conductive layer, and a stacked layer structure including the second conductive layer, the second insulating layer and the third conductive layer.
Thus, the present invention can realize a storage capacitor having a large capacitance value with occupying a small area in which variation in the capacitance value is greatly reduced. As a result, the invention provides a liquid crystal display device having a high aperture ratio (namely, high brightness) and high picture quality.
Also, since the liquid crystal display device of this invention has a simple structure, the fabrication procedures can be simplified, so that a liquid crystal display device having high picture quality can be fabricated at low cost and high yield. The liquid crystal display device of this invention is suitably applied to a comparatively compact and highly refined liquid crystal display device using polysilicon as a semiconductor layer of a TFT.